Product overview
The LUOWAVE LW-E320 is an embedded SDR terminal for wireless communications research, field testing and embedded applications. Its AD9361 transceiver provides two transmit and two receive channels with 2x2 MIMO operation, covering 70 MHz to 6 GHz with instantaneous bandwidth up to 56 MHz. Baseband processing combines a Xilinx Zynq-7045 SoC, FPGA acceleration and a dual-core ARM CPU for independent or collaborative operation. Preselector filter banks and 12-bit ADC and DAC conversion complete the radio architecture, while dual 10G SFP+ interfaces provide network connectivity.
The terminal occupies 173 x 106 x 45 mm and has maximum power consumption of 30 W. Its supplied software configuration includes customized Linux and open-source UHD 4.0 or higher, with GNU Radio support and development interfaces for MATLAB, Python, C# and C/C++. It supports external clock and PPS timing references; GPSDO is optional. Integration must accommodate the 0–45°C operating temperature range and 10%–90% operating humidity range. Storage limits are −40–85°C and 5%–95% humidity. Maximum receive bandwidth is 56 MHz, and maximum host PC sampling rate is 61.44 MS/s.
Specifications
| Specification | Value & conditions |
|---|---|
| Product identity and format | LUOWAVE LW-E320 standalone embedded software-defined radio terminal |
| RF transceiver | AD9361 |
| RF channels | 2 transmit channels and 2 receive channels |
| Frequency range | 70MHz – 6GHz |
| Maximum receive signal bandwidth | 56MHz |
| Baseband processing architecture | Xilinx Zynq-7045 SoC with FPGA acceleration and a dual-core ARM CPU |
| Network interfaces | Dual 10G SFP+ network interfaces |
| Application framework compatibility | Fully compatible with the Ettus USRP E320 application framework |
| RF filtering | Preselector filter banks |
| Supplied operating system | Preinstalled customized Linux operating system |
| External synchronization support | External clock reference and PPS timing reference support |
| GPSDO | Optional GPSDOOptional equipment. |
| Included UHD software | Built-in open-source UHD 4.0 or higher |
| Level at typical noise figure | -20 DBMAt typical noise figure. |
| DC input voltage and current | 10-14 V, 3 EN |
| Maximum output power | Greater than 10 DBM |
| Maximum power consumption | 30W |
| Receiver noise figure | Less than 8.5 dB |
| Dimensions | 173 x 106 x 45 mm |
| Maximum ADC sampling rate | 61.44 MSPS |
| Operating temperature range | 0-45° C. |
| ADC resolution | 12 bit |
| Storage temperature range | -40-85° C. |
| DAC sampling rate | 61.44 MSPS |
| Operating humidity range | 10%-90% |
| DAC resolution | 12 bit |
| Storage humidity range | 5%-95% |
| Maximum host PC sampling rate | 61.44MS/sHost PC operation. |
| Development environments and interfaces | Open-source GNU Radio environment support and auxiliary development interfaces for MATLAB, Python, C#, and C/C++ |
| FPGA development framework | FPGA development framework supporting RF network control |
