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LUOWAVE LW-B210

By Wuhan Tabebuia Technology Co., Ltd ↗

The LUOWAVE LW-B210 is a dual-channel software-defined radio combining an AD9361 RF front-end, programmable Xilinx FPGA and USB 3.0 connectivity. It covers 70 MHz to 6 GHz with maximum real-time bandwidth of 56 MHz per channel, with board, module and integrated-chassis configurations.

LUOWAVE LW-B210 software-defined radio in a blue enclosure with its connector panel visible
LUOWAVE LW-B210 software-defined radio in a blue enclosure with its connector panel visible
Model and radio architectureLUOWAVE LW-B210 dual-channel software-defined radio with 2 TX/RX channels and an AD9361 RF front-end
RF frequency range70 MHz to 6 GHz
Maximum real-time bandwidth56MHzPer channel.
Host interfaceUSB 3.0
FPGA configurationsXilinx Spartan-6 FPGA module; Xilinx Artix 7 200T FPGA module; Xilinx Artix 7 100T FPGA board only
Physical formatsBoard, module and integrated chassis

Product overview

The LUOWAVE LW-B210 provides two transmit/receive channels for software-defined radio operation, combining an AD9361 RF front-end with a programmable Xilinx FPGA. Its RF coverage extends from 70 MHz to 6 GHz, with maximum real-time bandwidth of 56 MHz per channel. USB 3.0 provides the host interface for use with various SDR frameworks. Both ADC and DAC resolution are 12 bits, with maximum ADC sampling and DAC sampling specified at 61.44 MSps; maximum 16-bit host transfer is also 61.44 MSps.

Physical configurations include Spartan-6 and Artix 7 200T modules, an Artix 7 100T board-only version, and an integrated chassis. The A7 100T board measures 17.2*10 cm and weighs 0.11kg; the chassis measures 23.5*30*8.5 cm and weighs 2.8kg. Chassis-specific equipment comprises an I7 8700 processor and 16G memory, with 220V power and 3A maximum current. The radio specifies a 6V DC input. TCXO accuracy depends on GPS state: less than 1ppb when locked and ±75ppb when unlocked.

Specifications

SpecificationValue & conditions
Model and radio architectureLUOWAVE LW-B210 dual-channel software-defined radio with 2 TX/RX channels and an AD9361 RF front-end
RF frequency range70 MHz to 6 GHz
Maximum real-time bandwidth56MHzPer channel.
Host interfaceUSB 3.0
FPGA configurationsXilinx Spartan-6 FPGA module; Xilinx Artix 7 200T FPGA module; Xilinx Artix 7 100T FPGA board only
Physical formatsBoard, module and integrated chassis
DC voltage input6V
TCXO accuracy with GPS lockLess than 1ppbGPS locked.
Maximum ADC sampling rate61.44 MSps
Single-sideband mirroring / LO rejection-40/-50dBcAt 1GHz.
ADC resolution12 bits
1GHz phase noise-102dBc/Hz@10KHzAt 1GHz, with a 10KHz offset.
ADC wideband SFDR78dBc
5GHz phase noise-91dBc/Hz@10KHzAt 5GHz, with a 10KHz offset.
DAC sampling rate61.44 MSps
Output power16dBm
DAC resolution12 bits
IIP3-20dBm
Maximum transfer rate with host61.44 MSps16-bit host transfer.
Noise figureLess than 8.5dB
Local oscillator accuracy±2.0ppm
TCXO accuracy without GPS lock±75ppbGPS unlocked.
ProcessorI7 8700Integrated chassis only.
Memory16GIntegrated chassis only.
Voltage220VIntegrated chassis only.
Maximum current3A MAXIntegrated chassis only.
Configuration masses
  • Spartan6: 0.695kg;
  • A7 200T: 0.8kg;
  • A7 100T: 0.11kg;
  • integrated chassis: 2.8kg
Spartan6, A7 200T, A7 100T and integrated chassis configurations, respectively.
Configuration dimensions
  • Spartan6: 17.5*10*1.7cm;
  • A7 200T: 17.9*12.7*4.8 cm;
  • A7 100T: 17.2*10 cm;
  • integrated chassis: 23.5*30*8.5 cm
Spartan6, A7 200T, A7 100T and integrated chassis configurations, respectively.

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