Product overview
The Forlinx Embedded FET3519A-C is an image-processing core board for camera systems, including aerial-imaging UAV applications. Its Hi3519AV100 processor combines two Cortex-A53 cores at 1.5GHz with 2GB DDR4 memory and 8GB eMMC storage. The 60 × 40mm module uses an eight-layer PCB with an immersion-gold finish and an ultra-thin board-to-board connector. Its operating supply is 5V, its temperature range is 0 °C to +70 °C, and its software configuration is Linux4.9.37+QT5.9. New-project selection is discouraged because of chip procurement lead times and other reasons.
Video integration includes H.265/H.264 encoding and decoding up to 4K × 2K at 60fps or 1080p at 240fps, plus 4K RAW output. The core-board functional parameters are hardware-design or CPU theoretical values: these include 12 input lanes, up to five sensors and maximum input resolution of 7680 × 4320. Ethernet, USB, PCIe and serial interfaces provide peripheral integration options. PCIe shares its interface with USB3.0, while LCD, BT.656 and BT.1120 are multiplexed so that only one can operate at a time.
Specifications
| Specification | Value & conditions |
|---|---|
| New-project selection limitation | Not recommended for selection in new projects because of chip procurement lead times and other reasons. |
| Processor | Hi3519AV100; dual-core Cortex-A53; 1.5GHz. |
| Memory and storage | 2GB DDR4 RAM; 8GB eMMC storage. |
| Operating system | Linux4.9.37+QT5.9. |
| Operating voltage | 5V. |
| Operating temperature | 0 °C to +70 °C. |
| Mechanical dimensions | 60 × 40mm. |
| Board connection | Ultra-thin board-to-board connector. |
| Functional parameter qualification | The core-board functional parameters are hardware-design or CPU theoretical values.Core-board functional parameters. |
| Video encoding, decoding and RAW output | H.265/H.264 encoding and decoding up to 4K × 2K@60fps / 1080p@240fps; 4K RAW output for film post-production. |
| Panorama stitching | Real-time 4K-class stitching of 2–4 video streams: two 3000 × 3000@30fps inputs or four 1080 × 1920@30fps inputs, producing 3840 × 2160@30fps output.Two or four simultaneous sensor inputs in the stated configurations. |
| Video input | 12 lanes; MIPI/sub-LVDS/HiSPI/SLVS-EC; up to 5 sensor inputs; maximum input resolution 7680 × 4320.Hardware-design or CPU theoretical values. |
| ISP | 1 ISP; AE/AWB/AF, fixed-pattern noise removal, WDR, highlight suppression, backlight compensation, defective-pixel correction and lens-shading correction.Hardware-design or CPU theoretical values; multiple video inputs share the ISP through time-division multiplexing. |
| SD/SDIO | ≤2 interfaces.Hardware-design or CPU theoretical values; SDIO0 supports SD2.0/3.0 and SDIO2.0/3.0; SDIO1 supports SDIO2.0/3.0. |
| USB2.0 | ≤1 interface; up to 480 Mbps.Hardware-design or CPU theoretical values; static switching between USB2.0 Host and USB2.0 Device. |
| USB3.0 | ≤1 interface; up to 5Gbps.Hardware-design or CPU theoretical values; static switching between USB3.0 Host and USB3.0 Device. |
| PCIe | ≤1 PCIe Gen2 ×1 controller; EP/RC modes.Hardware-design or CPU theoretical values; multiplexed with USB3.0. |
| UART | ≤9 interfaces; 9 UART controllers within the chip.Hardware-design or CPU theoretical values; UART0 is a two-wire port primarily for debugging; UART1/3/7/8 are four-wire; UART2/4/5/6 are two-wire. |
| SPI | ≤4 interfaces; chip provides 5 SPI groups; maximum output clock 50MHz; SPI, MicroWire and TI interfaces; single-frame and continuous-frame formats.Hardware-design or CPU theoretical values. |
| Three-wire SPI | ≤2 interfaces; chip provides 2 three-wire SPI interfaces.Hardware-design or CPU theoretical values; for connection to the MN34120 sensor. |
| IIC | ≤9 interfaces; 400Kbps transfer rate.Hardware-design or CPU theoretical values. |
| Ethernet | ≤1 interface; 10/100/1000Mbps auto-adaptive; RGMII and RMII modes.Hardware-design or CPU theoretical values. |
| PWM | ≤2 channels; 26-bit counter; selectable 3MHz, 24MHz or 50MHz clock source.Hardware-design or CPU theoretical values. |
| JTAG | Supported.Hardware-design or CPU theoretical values. |
| Audio | 1 integrated audio codec; 16bit voice input/output; dual-channel microphone input, single-ended or differential; IIS interface.Hardware-design or CPU theoretical values. |
| MIPI-DSI | 4 lanes; maximum 1080p@60fps.Hardware-design or CPU theoretical values. |
| LCD/BT.656/BT.1120 | ≤1 interface; LCD supports 24bit parallel, 16bit parallel, 6bit serial or 8bit serial output.Hardware-design or CPU theoretical values; LCD, BT.656 and BT.1120 are multiplexed, with only one usable at a time. |
| HDMI | 1 HDMI 2.0 interface; maximum 4K × 2K (4096 × 2160)@60fps output.Hardware-design or CPU theoretical values. |
| LSADC | ≤4 channels; 10bit sampling precision; 4 independent channels; scanning frequency ≤200K/s.Hardware-design or CPU theoretical values. |
| Infrared interface | ≤1 interface; decoding supports NEC with simple repeat code, NEC with full repeat code, SONY and TC9012 formats.Hardware-design or CPU theoretical values; mode 0 decodes data and mode 1 detects level width. |
Request a quote for FET3519A-C
Send your application, destination country and expected quantity to the ChinaDrone team. We can discuss product selection, configuration and sourcing from China.
Submit your procurement requirements ↗No account needed. A model number is optional. Your enquiry is handled by ChinaDrone.
